UEFI驱动代码

UEFI驱动模型

UEFI一个完整得驱动分为：

  • EFI Driver Binding Protocol
  • 驱动服务
  • EFI Component Protocol 为用户提供接口

EFI Driver Binding Protocol

结构体描述
  1. typedef struct _EFI_DRIVER_BINDING_PROTOCOL  EFI_DRIVER_BINDING_PROTOCOL;
  3. struct _EFI_DRIVER_BINDING_PROTOCOL {
  4.   EFI_DRIVER_BINDING_SUPPORTED  Supported;                        // 检测某一个设备是否支持该驱动
  5.   EFI_DRIVER_BINDING_START      Start;                                // 驱动安装接口
  6.   EFI_DRIVER_BINDING_STOP       Stop;                                    // 驱动卸载接口
  9.   UINT32                        Version;                            // EDBP版本号
  10.   EFI_HANDLE                    ImageHandle;                    // EDBP映像文件句柄
  11.   EFI_HANDLE                    DriverBindingHandle;    // 安装EDBP得Handle
  12. };

驱动加载接口

edk2\MdeModulePkg\Core\Dxe\Hand 目录提供了以下几个接口

  1. EFI_STATUS EFIAPI
  2. CoreConnectController (
  3.   IN  EFI_HANDLE                ControllerHandle,
  4.   IN  EFI_HANDLE                *DriverImageHandle    OPTIONAL,
  5.   IN  EFI_DEVICE_PATH_PROTOCOL  *RemainingDevicePath  OPTIONAL,
  6.   IN  BOOLEAN                   Recursive
  7.   );
  11. EFI_STATUS
  12. CoreConnectSingleController (
  13.   IN  EFI_HANDLE                ControllerHandle,
  14.   IN  EFI_HANDLE                *ContextDriverImageHandles OPTIONAL,
  15.   IN  EFI_DEVICE_PATH_PROTOCOL  *RemainingDevicePath       OPTIONAL
  16.   );
  18. EFI_STATUS 
  19. EFIAPI
  20. CoreDisconnectController (
  21.   IN  EFI_HANDLE  ControllerHandle,
  22.   IN  EFI_HANDLE  DriverImageHandle  OPTIONAL,
  23.   IN  EFI_HANDLE  ChildHandle        OPTIONAL
  24.   );

PCI驱动

协议注册

  1. //
  2. // PCI Bus Driver Global Variables
  3. //
  4. EFI_DRIVER_BINDING_PROTOCOL                   gPciBusDriverBinding = {
  5.   PciBusDriverBindingSupported,
  6.   PciBusDriverBindingStart,
  7.   PciBusDriverBindingStop,
  8.   0xa,
  9.   NULL,
  10.   NULL
  11. };

初始化代码

  1. PciBusDriverBindingStart
  2.     PciEnumerator
  3.         PciHostBridgeEnumerator

打印信息

  1. PCI Bus First Scanning
  2. PciBus: Discovered PCI @ [00|00|00]
  4. PciBus: Discovered PCI @ [00|01|00]
  6. PciBus: Discovered PCI @ [00|01|01]
  7.    BAR[4]: Type =   Io32; Alignment = 0xF;  Length = 0x10;  Offset = 0x20
  9. PciBus: Discovered PCI @ [00|01|03]
  11. PciBus: Discovered PCI @ [00|02|00]
  12.    BAR[0]: Type = PMem32; Alignment = 0xFFFFFF; Length = 0x1000000; Offset = 0x10
  13.    BAR[2]: Type =  Mem32; Alignment = 0xFFF;    Length = 0x1000;    Offset = 0x18
  15. PciBus: Discovered PCI @ [00|03|00]
  16.    BAR[0]: Type =  Mem32; Alignment = 0x1FFFF;  Length = 0x20000;   Offset = 0x10
  17.    BAR[1]: Type =   Io32; Alignment = 0x3F; Length = 0x40;  Offset = 0x14
  19. PCI Bus Second Scanning
  20. PciBus: Discovered PCI @ [00|00|00]
  22. PciBus: Discovered PCI @ [00|01|00]
  24. PciBus: Discovered PCI @ [00|01|01]
  25.    BAR[4]: Type =   Io32; Alignment = 0xF;  Length = 0x10;  Offset = 0x20
  27. PciBus: Discovered PCI @ [00|01|03]
  29. PciBus: Discovered PCI @ [00|02|00]
  30.    BAR[0]: Type = PMem32; Alignment = 0xFFFFFF; Length = 0x1000000; Offset = 0x10
  31.    BAR[2]: Type =  Mem32; Alignment = 0xFFF;    Length = 0x1000;    Offset = 0x18
  33. PciBus: Discovered PCI @ [00|03|00]
  34.    BAR[0]: Type =  Mem32; Alignment = 0x1FFFF;  Length = 0x20000;   Offset = 0x10
  35.    BAR[1]: Type =   Io32; Alignment = 0x3F; Length = 0x40;  Offset = 0x14                                                                                                                                                                   
  37. PciBus: Discovered PCI @ [00|00|00]
  39. PciBus: Discovered PCI @ [00|01|00]
  42. PciBus: Discovered PCI @ [00|01|01]
  43.    BAR[4]: Type =   Io32; Alignment = 0xF;  Length = 0x10;  Offset = 0x20
  45. PciBus: Discovered PCI @ [00|01|03]
  47. PciBus: Discovered PCI @ [00|02|00]
  48.    BAR[0]: Type = PMem32; Alignment = 0xFFFFFF; Length = 0x1000000; Offset = 0x10
  49.    BAR[2]: Type =  Mem32; Alignment = 0xFFF;    Length = 0x1000;    Offset = 0x18
  51. PciBus: Discovered PCI @ [00|03|00]
  52.    BAR[0]: Type =  Mem32; Alignment = 0x1FFFF;  Length = 0x20000;   Offset = 0x10
  53.    BAR[1]: Type =   Io32; Alignment = 0x3F; Length = 0x40;  Offset = 0x14
  55. PciHostBridge: SubmitResources for PciRoot(0x0)
  56.  I/O: Granularity/SpecificFlag = 0 / 01
  57.       Length/Alignment = 0x1000 / 0xFFF
  58.  Mem: Granularity/SpecificFlag = 32 / 00
  59.       Length/Alignment = 0x1100000 / 0xFFFFFF
  60. PciBus: HostBridge->SubmitResources() - Success
  61. PciHostBridge: NotifyPhase (AllocateResources)
  62.  RootBridge: PciRoot(0x0)
  63.   Mem: Base/Length/Alignment = 80000000/1100000/FFFFFF - Success
  64.   I/O: Base/Length/Alignment = C000/1000/FFF - Success
  65. PciBus: HostBridge->NotifyPhase(AllocateResources) - Success
  66. PciBus: Resource Map for Root Bridge PciRoot(0x0)
  67. Type =   Io16; Base = 0xC000;   Length = 0x1000;    Alignment = 0xFFF
  68.    Base = 0xC000;   Length = 0x40;  Alignment = 0x3F;   Owner = PCI [00|03|00:14]
  69.    Base = 0xC040;   Length = 0x10;  Alignment = 0xF;    Owner = PCI [00|01|01:20]
  70. Type =  Mem32; Base = 0x80000000;   Length = 0x1100000; Alignment = 0xFFFFFF
  71.    Base = 0x80000000;   Length = 0x1000000; Alignment = 0xFFFFFF;   Owner = PCI [00|02|00:10]; Type = PMem32
  72.    Base = 0x81000000;   Length = 0x20000;   Alignment = 0x1FFFF;    Owner = PCI [00|03|00:10]
  73.    Base = 0x81020000;   Length = 0x1000;    Alignment = 0xFFF;  Owner = PCI [00|02|00:18]