本文介绍了ahb_ram验证环境的搭建及其具体代码

1.1 波形理解

image.png

  • 先看T4-T7拍，可以发现：T4拍写入的地址为0x28，T5拍Ready信号为低，slave一侧没有做好接收数据的准备，因此data等了一拍以后才写出去，从之前的波形中可以看出来，data正常都是等了一拍以后才会写出去，因此在t4拍开始等了两拍，在第三拍的时候才将数据成功发送。

    1.1 搭建VIP_lib框架

    1.1.1 ahb_agent框架搭建

    :::danger 【思考】
    为了验证AHB_RAM的设计代码，其接口类型是AHB的，为了通过这个AHB给DUT给定测试激励，首先需要agent来在环境中帮助给出激励，而这个agent需要VIP来提供，因此我们需要使用到AHB这个协议，此部分来实现VIP。 ::: image.png

    其中ahb_driver_common.sv用来防止一些公共的驱动； ahb_types用来放置一些公共的类型； 之所以有一些类名前没有master，是因为之后slave和master可能有相同的部分，因此都需要继承同一个公共的类。

:::info （1）在ahb_pkg中导入VIP文件； :::

  1. `ifndef AHB_PKG_SV
  2. `define AHB_PKG_SV
  4. package ahb_pkg;
  6.   import uvm_pkg::*;
  7.   `include "uvm_macros.svh"
  9.   `include "ahb_defines.svh"
  10.   `include "ahb_types.sv"
  11.   `include "ahb_transaction.sv"
  12.   `include "ahb_sequencer.sv"
  13.   `include "ahb_driver.sv"
  14.   `include "ahb_monitor.sv"
  15.   `include "ahb_master_transaction.sv"
  16.   `include "ahb_master_sequencer.sv"
  17.   `include "ahb_master_driver.sv"
  18.   `include "ahb_master_monitor.sv"
  19.   `include "ahb_master_agent.sv"
  21. endpackage
  23. `endif // AHB_PKG_SV

:::info （2）ahb_driver & ahb_master_driver ::: :::danger 【注】
对于driver和sequencer参数类而言，由于在master和slave中可能传递的是不同的transaction，因此这里应当在父类中给定参数的传递： :::

  1. `ifndef AHB_DRIVER_SV
  2. `define AHB_DRIVER_SV
  4. class ahb_driver #(type REQ = ahb_transaction, type RSP = REQ) extends uvm_driver #(REQ, RSP);
  6.   `uvm_component_utils(ahb_driver)
  8.   function new (string name = "ahb_driver", uvm_component parent = null);
  9.     super.new(name, parent);
  10.   endfunction
  12.   function build_phase(uvm_phase phase);
  13.     super.build_phase(phase);
  14.   endfunction
  16.   function connect_phase(uvm_phase phase);
  17.     super.connect_phase(phase);
  18.   endfunction
  20.   task run_phase(uvm_phase phase);
  21.     super.run_phase(phase);
  22.     phase.raise_objection(phase);
  23.     phase.drop_objection(phase);
  24.   endtask
  26. endclass
  28. `endif // AHB_DRIVER_SV

1.1.2 参数类问题

ahb_driver作为父类而言，不仅不能做参数，还应当保留参数。使得继承于它的子类可以将这些属性保留下来

image.png

  • uvm_sequencer首先应该是一个参数类，所以紧跟它有一个#；
  • 同时，为了将REQ和RSQ在这一层子类的类型传导到父类，所以在后面加了第二个#。

  • 第一个#是声明参数，第二个#是参数的传导/给定。

  • 需要将参数传导至上一层的原因是，父类中传递的事物是uvm_sequence_item类型的，而driver中传递的事物是ahb_transaction类型的。

:::info （3）编辑参数类ahb_sequencer & ahb_master_sequencer :::

  1. `ifndef AHB_SEQUENCER_SV
  2. `define AHB_SEQUENCER_SV
  4. class ahb_sequencer #(type REQ = ahb_transaction, type RSP = REQ) extends uvm_sequencer #(REQ, RSP);
  6.   `uvm_component_utils(ahb_sequencer)
  8.   function new (string name = "ahb_sequencer", uvm_component parent = null);
  9.     super.new(name,parent);
  10.   endfunction
  12.   function void build_phase(uvm_phase phase);
  13.     super.build_phase(phase);
  14.   endfunction
  16.   function void connect_phase(uvm_phase phase);
  17.     super.connect_phase(phase);
  18.   endfunction
  20.   task run_phase(uvm_phase phase);
  21.     super.run_phase(phase);
  22.   endtask
  24. endclass
  26. `endif // AHB_SEQUENCER_SV
  1. `ifndef AHB_MASTER_SEQUENCER_SV
  2. `define AHB_MASTER_SEQUENCER_SV
  4. class ahb_master_sequencer extends ahb_sequencer;
  6.   `uvm_component_utils(ahb_master_sequencer)
  8.   function new (string name = "ahb_master_sequencer", uvm_component parent = null);
  9.     super.new(name,parent);
  10.   endfunction
  12.   function void build_phase(uvm_phase phase);
  13.     super.build_phase(phase);
  14.   endfunction
  16.   function void connect_phase(uvm_phase phase);
  17.     super.connect_phase(phase);
  18.   endfunction
  20.   task run_phase(uvm_phase phase);
  21.     super.run_phase(phase);
  22.   endtask
  24. endclass
  26. `endif // AHB_MASTER_SEQUENCER_SV

:::info （4）编辑ahb_monitor & ahb_master_monitor :::

  1. `ifndef AHB_MONITOR_SV
  2. `define AHB_MONITOR_SV
  4. class ahb_monitor extends uvm_monitor;
  6.   `uvm_component_utils(ahb_monitor)
  8.   function new (string name = "ahb_monitor", uvm_component parent = null);
  9.     super.new(name,parent);
  10.   endfunction
  12.   function void build_phase(uvm_phase phase);
  13.     super.build_phase(phase);
  14.   endfunction
  16.   function void connect_phase(uvm_phase phase);
  17.     super.connect_phase(phase);
  18.   endfunction
  20.   task run_phase(uvm_phase phase);
  21.     super.run_phase(phase);
  22.   endtask
  24. endclass
  26. `endif // AHB_MONITOR_SV
  1. `ifndef AHB_MASTER_MONITOR_SV
  2. `define AHB_MASTER_MONITOR_SV
  4. class ahb_master_monitor extends ahb_monitor;
  6.   `uvm_component_utils(ahb_master_monitor)
  8.   function new (string name = "ahb_master_monitor", uvm_component parent = null);
  9.     super.new(name, parent);
  10.   endfunction
  12.   function void build_phase(uvm_phase phase);
  13.     super.build_phase(phase);
  14.   endfunction
  16.   function void connect_phase(uvm_phase phase);
  17.     super.connect_phase(phase);
  18.   endfunction
  20.   task run_phase(uvm_phase phase);
  21.     super.run_phase(phase);
  22.   endtask
  24. endclass
  26. `endif // AHB_MASTER_MONITOR_SV

:::info （5）编辑configuration及agent_configuration :::

  1. `ifndef AHB_CONFIGURATION_SV
  2. `define AHB_CONFIGURATION_SV
  4. class ahb_configuration extends uvm_object;
  6.   `uvm_object_utils_begin(ahb_configuration)
  7.   `uvm_object_utils_end
  9.   function new (string name = "ahb_configuration");
  10.     super.new(name);
  11.   endfunction
  12. endclass
  14. `endif // AHB_CONFIGURATION_SV

config文件不仅要对ahb进行配置，还需要对ahb_vip中的agent进行配置。

:::info （6）Makefile文件 ::: image.png :::danger 【思考】

  1. 搭好了框架以后如何让AHB开始工作？AHB在ENV中应该给出什么样的激励给DUT？
  2. 给AHB_RAM供给什么数据内容？ :::

    1.1.3 VIP_lib补充

    注：实际上对于VIP_lib的补充是发生在env连接关系之后的，根据移植过来的env环境来对vip_lib中的各个组件进行修改。 :::info 根据env中的连接关系：
  • 虽然在env中是ahb_mst_monitor上的port连接到了predictor上，实际上mst_monitor和slave_monitor都会监测数据，所以将这个port放在ahb_monitor上，使得继承于它的子类都能够使用该port。 ::: ``verilogifndef AHB_MONITOR_SV `define AHB_MONITOR_SV

class ahb_monitor extends uvm_monitor;

uvm_analysis_port #(ahb_transaction) item_observed_port;

`uvm_component_utils(ahb_monitor)

function new (string name = “ahb_monitor”, uvm_component parent = null); super.new(name,parent); item_observed_port = new(“item_observed_port”, this); endfunction

function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction

function void connect_phase(uvm_phase phase); super.connect_phase(phase); endfunction

task run_phase(uvm_phase phase); super.run_phase(phase); endtask

endclass

`endif // AHB_MONITOR_SV

  1. :::info
  2. （2）在env的connect_phase中，有许多port连接到了组件上，因此需要在agent中对组件进行例化：
  4. - 在agent中声明config和vif，并在build_phase中从上层拿到cfg和vif；
  5. - 在agent中声明组件并在build_phase中例化；
  6. - 在connect_phase中完成driver和sequencer之间端口的连接，将vif与子一级的组件之间进行连接
  7. :::
  8. :::info
  9. 【补充】<br />根据标准的VIP_lib，在ahb_agent_configuration中需要声明is_active变量，作用是对driver和monitor进行开关控制。
  10. :::
  11. ```verilog
  12. `ifndef AHB_MASTER_AGENT_SV
  13. `define AHB_MASTER_AGENT_SV
  15. class ahb_master_agent extends uvm_agent;
  17.   ahb_agent_configuration cfg;
  19.   ahb_master_driver driver;
  20.   ahb_master_monitor monitor;
  21.   ahb_master_sequencer sequencer;
  23.   virtual ahb_if vif;
  25.   `uvm_component_utils(ahb_master_agent)
  27.   function new (string name = "ahb_master_agent", uvm_component parent = null);
  28.     super.new(name, parent);
  29.   endfunction
  31.   function void build_phase(uvm_phase phase);
  32.     super.build_phase(phase);
  34.     if(!uvm_config_db #(ahb_agent_configuration)::get(this, "", "cfg", cfg) begin
  35.       `uvm_fatal("GETCFG", "cannot get ahb_agent_configuration")
  36.     end
  38.     if(!uvm_config_db #(ahb_if)::get(this, "", "vif", vif) begin
  39.       `uvm_fatal("GETVIF", "cannot get vif")
  40.     end
  42.     monitor = ahb_master_monitor::type_id::create("monitor", this);
  44.     if(cfg.is_active) begin
  45.       driver = ahb_master_driver::type_id::create("driver", this);
  46.       sequencer = ahb_master_sequencer::type_id::create("sequencer", this);
  47.     end
  49.   endfunction
  51.   function void connect_phase(uvm_phase phase);
  52.     super.connect_phase(phase);
  53.     if(cfg.is_active) begin
  54.       driver.seq_item_port.connect(sequencer.seq_item_export);
  55.       driver.vif = vif;
  56.       monitor.vif = vif;
  57.       sequencer.vif = vif;
  58.     end
  59.   endfunction
  61.   task run_phase(uvm_phase phase);
  62.     super.run_phase(phase);
  63.   endtask
  65. endclass
  67. `endif // AHB_MASTER_AGENT_SV
  1. `ifndef AHB_MASTER_DRIVER_SV
  2. `define AHB_MASTER_DRIVER_SV
  4. class ahb_master_driver extends ahb_driver;
  6.   ahb_agent_configuration cfg;
  7.   virtual ahb_if vif;
  9.   `uvm_component_utils(ahb_master_driver)
  11.   function new (string name = "ahb_master_driver", uvm_component parent = null);
  12.     super.new(name, parent);
  13.   endfunction
  15.   function void build_phase(uvm_phase phase);
  16.     super.build_phase(phase);
  17.   endfunction
  19.   function void connect_phase(uvm_phase phase);
  20.     super.connect_phase(phase);
  21.   endfunction
  23.   task run_phase(uvm_phase phase);
  24.     super.run_phase(phase);
  25.   endtask
  27. endclass
  29. `endif // AHB_MASTER_DRIVER_SV
  1. `ifndef AHB_MASTER_MONITOR_SV
  2. `define AHB_MASTER_MONITOR_SV
  4. class ahb_master_monitor extends ahb_monitor;
  6.   ahb_agent_configuration cfg;
  7.   virtual ahb_if vif;
  9.   `uvm_component_utils(ahb_master_monitor)
  11.   function new (string name = "ahb_master_monitor", uvm_component parent = null);
  12.     super.new(name, parent);
  13.   endfunction
  15.   function void build_phase(uvm_phase phase);
  16.     super.build_phase(phase);
  17.   endfunction
  19.   function void connect_phase(uvm_phase phase);
  20.     super.connect_phase(phase);
  21.   endfunction
  23.   task run_phase(uvm_phase phase);
  24.     super.run_phase(phase);
  25.   endtask
  27. endclass
  29. `endif // AHB_MASTER_MONITOR_SV

1.2 ahb_ram顶层环境搭建及仿真

1.2.1 env一侧代码

:::danger 之前已经完成了agent框架的搭建，接下来需要搭建ahb_ram的上层环境，在env中例化agent并运行仿真，在仿真中观察验证结构是什么样的。 ::: :::info （1）ahb_ram_virt_sequencer.sv文件编辑 :::

  1. `ifndef AHB_RAM_VIRTUAL_SEQUENCER_SV
  2. `define AHB_RAM_VIRTUAL_SEQUENCER_SV
  4.   class ahb_ram_virtual_sequencer extends uvm_sequencer;
  6.     ahb_master_sequencer ahb_mst_sqr;
  7.     ahb_ram_config cfg;
  9.     `uvm_component_utils(ahb_ram_virtual_sequencer)
  11.     function new(string name = "ahb_ram_virtual_sequencer", uvm_component parent);
  12.       super.new(name, parent);
  13.     endfunction
  15.     function void build_phase(uvm_phase phase);
  16.       super.build_phase(phase);
  17.       //Get configuration from env layer
  18.       uvm_config_db#(ahb_ram_config)::get(this, "", "cfg", cfg);
  19.     endfunction
  21.   endclass
  23. `endif //AHB_RAM_VIRTUAL_SEQUENCER

:::info （2）env中已经例化了ahb_config文件，所以此处对ahb_config文件进行编辑：

  • 声明并例化ahb_vip中的config；
  • 在config中声明vif的句柄。 ::: ``verilogifndef AHB_RAM_CONFIG_SV `define AHB_RAM_CONFIG_SV

class ahb_ram_config extends uvm_object;

int seq_check_count; int seq_check_error;

int scb_check_count; int scb_check_error;

bit scb_enable = 1; bit cov_enable = 1;

ahb_configuration ahb_cfg; virtual ahb_ram_if vif;

`uvm_object_utils(ahb_ram_config)

// USER to specify the config items

function new (string name = “ahb_ram_config”); super.new(name); ahb_cfg = ahb_configuration::type_id::create(“ahb_cfg”); endfunction : new

endclass `endif // AHB_RAM_CONFIG_SV

  1. > config中配置了用于控制scoreboard和coverage的开关。
  3. :::info
  4. （3）在config中配置了用于控制scoreboard和coverage的开关，因此需要对subscriber编辑：
  5. :::
  6. ```verilog
  7. `ifndef AHB_RAM_SUBSCRIBER_SV
  8. `define AHB_RAM_SUBSCRIBER_SV
  10. `uvm_analysis_imp_decl(_apb)
  12. class ahb_ram_subscriber extends uvm_component;
  14.   // analysis import
  15.   uvm_analysis_imp #(ahb_transaction, ahb_ram_subscriber) ahb_trans_observed_imp; 
  17.   // Declare events
  19.   ahb_ram_config cfg;
  20.   virtual ahb_ram_if vif;
  22.   `uvm_component_utils(ahb_ram_subscriber)
  24.   function new(string name = "ahb_ram_subscriber", uvm_component parent);
  25.     super.new(name, parent);
  26.   endfunction
  28.   function void build_phase(uvm_phase phase);
  29.     super.build_phase(phase);
  30.     apb_trans_observed_imp = new("apb_trans_observed_imp", this);
  31.     // Get configuration from test layer
  32.     if(!uvm_config_db#(ahb_ram_config)::get(this, "", "cfg", cfg)) begin
  33.       `uvm_fatal("GETCFG", "cannot get conifg object from config db")
  34.     end
  35.     vif = cfg.vif;
  36.   endfunction 
  38.   task run_phase(uvm_phase phase);
  39.     super.run_phase(phase);
  40.     do_events_trigger();
  41.     do_listen_events();
  42.   endtask
  44.   virtual function void write(ahb_transaction tr);
  45.   endfunction
  47.   virtual task do_events_trigger();
  48.   endtask
  50.   virtual task do_listen_events();
  51.   endtask
  53. endclass
  55. `endif // AHB_RAM_SUBSCRIBER_SV

:::info （4）suscriber中监听了来自monitor的数据，scoreboard对采集到的数据进行比较： :::

  1. `ifndef AHB_RAM_SCOREBOARD_SV
  2. `define AHB_RAM_SCOREBOARD_SV
  4. class ahb_ram_scoreboard extends ahb_ram_subscriber;
  6.   // Events of scoreboard
  8.   `uvm_component_utils(ahb_ram_scoreboard)
  10.   function new (string name = "ahb_ram_scoreboard", uvm_component parent);
  11.     super.new(name, parent);
  12.   endfunction
  14.   function void build_phase(uvm_phase phase);
  15.     super.build_phase(phase);
  16.   endfunction
  18.   task run_phase(uvm_phase phase);
  19.     super.run_phase(phase);
  20.     do_countdown_check();
  21.   endtask
  23.   task do_listen_events();
  24.   endtask
  26.   virtual task do_data_check();
  27.   endtask
  29. endclass
  31. `endif // AHB_RAM_SCOREBOARD_SV

:::info （5）编辑ahb_ram的coverage文件 :::

  1. `ifndef AHB_RAM_COV_SV
  2. `define AHB_RAM_COV_SV
  4. class ahb_ram_cov extends ahb_ram_subscriber;
  6.   `uvm_component_utils(ahb_ram_cov)
  8.   // Covergroup definition below
  10.   function new (string name = "ahb_ram_cov", uvm_component parent);
  11.     super.new(name, parent);
  12.   endfunction
  14.   function void build_phase(uvm_phase phase);
  15.     super.build_phase(phase);
  16.   endfunction
  18.   task do_listen_events();
  19.   endtask
  21. endclass
  23. `endif // AHB_RAM_COV_SV

:::info （6）寄存器模型编辑：
在生成寄存器模型的时候也需要将map声明到寄存器模型中 :::

  1. `ifndef AHB_RAM_REG_SV
  2. `define AHB_RAM_REG_SV
  4. class ahb_ram_rgm extends uvm_object;
  6.   `uvm_object_utils(ahb_ram_rgm)
  8.   uvm_reg_map map;
  10.   function new (string name = "ahb_ram_rgm");
  11.     super.new(name);
  12.   endfunction
  14.   virtual function build();
  15.     map = create_map("map", 'h0, 4, UVM_LITTLE_ENDIAN);
  16.   endfunction
  17. endclass
  19. `endif // AHB_RAM_REG_SV

:::info （7）有了寄存器模型，那么也相应需要adapter来进行寄存器模型和总线之间的访问：
adapter中暂时没有声明具体的方法来完成rgm_operation和bus_item之间的转换。 :::

  1. `ifndef AHB_RAM_ADAPTER_SV
  2. `define AHB_RAM_ADAPTER_SV
  4. class ahb_ram_adapter extends uvm_reg_adapter;
  6.     `uvm_object_utils(ahb_ram_adapter)
  8.     function new(string name = "ahb_ram_adapter");
  9.       super.new(name);
  10.     endfunction
  12.     function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
  13.     endfunction
  15.     function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
  16.     endfunction
  18.   endclass
  20. `endif //AHB_RAM_ADAPTER_SV

:::danger （7）在完成了上述组件的内容之后，最后一步就是将他们集成到env中： :::

  1. `ifndef AHB_RAM_ENV_SV
  2. `define AHB_RAM_ENV_SV
  4. class ahb_ram_env extends uvm_env;
  6.   ahb_master_agent ahb_mst;
  7.   ahb_ram_config cfg;
  8.   ahb_ram_virtual_sequencer virt_sqr;
  9.   ahb_ram_rgm rgm;
  10.   ahb_ram_adapter adapter;
  11.   uvm_reg_predictor #(ahb_transfer) predictor;
  12.   ahb_ram_cov cov;
  13.   ahb_ram_scoreboard scb;
  15.  `uvm_component_utils(ahb_ram_env)
  17.    function new (string name = "ahb_ram_env", uvm_component parent);
  18.     super.new(name, parent);
  19.   endfunction
  21.   function void build_phase(uvm_phase phase);
  22.     super.build_phase(phase);
  23.     // Get configuration from test layer
  24.     if(!uvm_config_db#(ahb_ram_config)::get(this,"","cfg", cfg)) begin
  25.       `uvm_fatal("GETCFG","cannot get config object from config DB")
  26.     end
  27.     uvm_config_db#(ahb_ram_config)::set(this, "virt_sqr", "cfg", cfg);
  28.     uvm_config_db#(ahb_ram_config)::set(this, "cov", "cfg", cfg);
  29.     uvm_config_db#(ahb_ram_config)::set(this, "scb", "cfg", cfg);
  30.     uvm_config_db#(ahb_agent_configuration)::set(this, "ahb_mst", "cfg", cfg.ahb_cfg);
  31.     ahb_mst = ahb_master_agent::type_id::create("ahb_mst", this);
  32.     virt_sqr = ahb_ram_virtual_sequencer::type_id::create("virt_sqr", this);
  33.     if(!uvm_config_db#(ahb_ram_rgm)::get(this,"","rgm", rgm)) begin
  34.       rgm = ahb_ram_rgm::type_id::create("rgm", this);
  35.       rgm.build();
  36.     end
  37.     uvm_config_db#(ahb_ram_rgm)::set(this, "*", "rgm", rgm);
  38.     adapter = ahb_ram_adapter::type_id::create("adapter");
  39.     predictor = uvm_reg_predictor#(ahb_transfer)::type_id::create("predictor", this);
  40.     scb = ahb_ram_scoreboard::type_id::create("scb", this);
  41.     cov = ahb_ram_cov::type_id::create("cov", this);
  42.   endfunction
  44.   function void connect_phase(uvm_phase phase);
  45.     super.connect_phase(phase);
  46.     virt_sqr.ahb_mst_sqr = ahb_mst.sequencer; 
  47.     rgm.map.set_sequencer(ahb_mst.sequencer, adapter);
  48.     ahb_mst.monitor.item_observed_port.connect(predictor.bus_in);
  49.     predictor.map = rgm.map;
  50.     predictor.adapter = adapter;
  51.     ahb_mst.monitor.item_observed_port.connect(cov.ahb_trans_observed_imp);
  52.     ahb_mst.monitor.item_observed_port.connect(scb.ahb_trans_observed_imp);
  53.   endfunction
  55.   function void report_phase(uvm_phase phase);
  56.     string reports = "\n";
  57.     super.report_phase(phase);
  58.     reports = {reports, $sformatf("================================================= \n")};
  59.     reports = {reports, $sformatf("CURRENT TEST SUMMARY \n")};
  60.     reports = {reports, $sformatf("SEQUENCE CHECK COUNT : %0d \n", cfg.seq_check_count)};
  61.     reports = {reports, $sformatf("SEQUENCE CHECK ERROR : %0d \n", cfg.seq_check_error)};
  62.     reports = {reports, $sformatf("SCOREBOARD CHECK COUNT : %0d \n", cfg.scb_check_count)};
  63.     reports = {reports, $sformatf("SCOREBOARD CHECK COUNT : %0d \n", cfg.scb_check_error)};
  64.     reports = {reports, $sformatf("=================================================")};
  65.     `uvm_info("TEST_SUMMARY",reports, UVM_LOW);
  66.   endfunction
  67. endclass
  69. `endif // AHB_RAM_ENV_SV

在env搭建这一步中，特别是在connect_phase这一步中，需要观察每一个组件中哪些部分进行了连接：

  1. rgm中map连接到了sequencer和adapter中，故需要在adapter中添加map；
  2. monitor的port连接到了predictor的bus_in上，故需要在monitor中声明port；

1.2.2 test一侧代码

:::info 新建ahb_ram_seq_lib.svh并将base_virt_seq和发烟_seq集成在内； :::

  1. `ifndef AHB_RAM_SEQ_LIB_SVH
  2. `define AHB_RAM_SEQ_LIB_SVH
  4.   `include "ahb_ram_base_virtual_seq.sv"
  5.   `include "ahb_ram_smoke_virt_seq.sv"
  7. `endif
  1. `ifndef AHB_RAM_BASE_VIRT_SEQ_SV
  2. `define AHB_RAM_BASE_VIRT_SEQ_SV
  4.   class ahb_ram_base_virt_seq extends uvm_sequence;
  6.     ahb_ram_config cfg;
  7.     virtual ahb_ram_if vif;
  8.     ahb_ram_rgm rgm;
  9.     bit [31:0] rd_val, wr_val;
  10.     uvm_status_e status;
  11.     `uvm_object_utils(ahb_ram_base_virt_seq)
  12.     `uvm_declare_p_sequencer(ahb_ram_virtual_sequencer)
  14.     function new(string name = "ahb_ram_base_virt_seq");
  15.       super.new(name);
  16.     endfunction
  18.     virtual task body();
  19.     `uvm_info("body","Entered...",UVM_LOW)
  20.       //Get cfg from p_sequencer
  21.       cfg = p_sequencer.cfg;
  22.       vif = cfg.vif;
  23.       rgm = cfg.rgm;
  24.     `uvm_info("body","Exiting...",UVM_LOW)
  25.     endtask
  27.     virtual function void compare_data(logic[31:0] val1, logic[31:0] val2);
  28.       cfg.seq_check_count++;
  29.      if(val1 === val2)
  30.        `uvm_info("CMPSUC", $sformatf("val1 'h%0x === val2 'h%0x", val1, val2), UVM_LOW)
  31.      else begin
  32.       cfg.seq_check_error++;
  33.        `uvm_error("CMPSUC", $sformatf("val1 'h%0x !== val2 'h%0x", val1, val2))
  34.      end
  35.     endfunction
  37.     task wait_reset_asserted();
  38.       @(posedge vif.rst_n);
  39.     endtask
  41.     task wait_reset_released();
  42.       @(negedge vif.rst_n);
  43.     endtask
  45.   endclass
  47. `endif //AHB_RAM_BASE_VIRT_SEQ
  1. `ifndef AHB_RAM_SMOKE_VIRT_SEQ_SV
  2. `define AHB_RAM_SMOKE_VIRT_SEQ_SV
  4.   class ahb_ram_smoke_virt_seq extends apb_watchdog_base_virt_seq;
  6.     `uvm_object_utils(ahb_ram_smoke_virt_seq)
  8.     function new(string name = "ahb_ram_smoke_virt_seq");
  9.       super.new(name);
  10.     endfunction
  12.     virtual task body();
  13.       super.body();
  14.       `uvm_info("body","Entered...",UVM_LOW)
  15.       `uvm_info("body","EXited...", UVM_LOW)
  16.     endtask
  18.   endclass
  20. `endif //AHB_RAM_SMOKE_VIRT_SEQ_SV

:::info 在test一层中补充对应的test文件：

  • apb_ram_base_test.sv
  • apb_ram_smoke_test.sv ::: ``verilogifndef AHB_RAM_BASE_TEST_SV `define AHB_RAM_BASE_TEST_SV

virtual class ahb_ram_base_test extends uvm_test;

  1. ahb_ram_config cfg;
  2. ahb_ram_env env;
  3. ahb_ram_rgm rgm;
  5. function new(string name = "ahb_ram_base_test", uvm_component parent);
  6.   super.new(name, parent);
  7. endfunction
  9. function void build_phase(uvm_phase phase);
  10.   super.build_phase(phase);
  11.   rgm = ahb_ram_rgm::type_id::create("rgm");
  12.   rgm.build();
  13.   uvm_config_db#(ahb_ram_rgm)::set(this, "env", "rgm", rgm);
  14.   cfg = ahb_ram_config::type_id::create("cfg");
  15.   cfg.rgm = rgm;
  16.   if(!uvm_config_db#(virtual ahb_ram_if)::get(this,"","vif", cfg.vif)) begin
  17.     `uvm_fatal("GETCFG","cannot get virtual interface from config DB")
  18.   end
  19.   uvm_config_db#(ahb_ram_config)::set(this, "env", "cfg", cfg);
  20.   env = ahb_ram_env::type_id::create("env", this);
  21. endfunction
  23. function void connect_phase(uvm_phase phase);
  24.   super.connect_phase(phase);
  25. endfunction
  27. task run_phase(uvm_phase phase);
  28.   super.run_phase(phase);
  29.   phase.phase_done.set_drain_time(this, 1us);
  30.   phase.raise_objection(this);
  31.   phase.drop_objection(this);
  32. endtask

endclass

`endif //AHB_RAM_BASE_TEST

  1. ```verilog
  2. `ifndef AHB_RAM_SMOKE_TEST_SV
  3. `define AHB_RAM_SMOKE_TEST_SV
  5. class ahb_ram_smoke_test extends apb_watchdog_base_test;
  7.     `uvm_component_utils(ahb_ram_smoke_test)
  9.     function new(string name = "ahb_ram_smoke_test", uvm_component parent);
  10.       super.new(name, parent);
  11.     endfunction
  13.     function void build_phase(uvm_phase phase);
  14.       super.build_phase(phase);
  15.     endfunction
  17.     task run_phase(uvm_phase phase);
  18.       ahb_ram_smoke_virt_seq seq = ahb_ram_smoke_virt_seq::type_id::create("this");
  19.       super.run_phase(phase);
  20.       phase.raise_objection(this);
  21.       seq.start(env.virt_sqr);
  22.       phase.drop_objection(this);
  23.     endtask
  25. endclass
  27. `endif //AHB_RAM_SMOKE_TEST_SV
  1. `ifndef AHB_RAM_TESTS_SVH
  2. `define AHB_RAM_TESTS_SVH
  4.   `include "ahb_ram_base_test.sv"
  5.   `include "ahb_ram_smoke_test.sv"
  7. `endif // AHB_RAM_TESTS_SVH

【调试及结果】

image.png

调试报错没有拿到vif

:::info 在tb中例化interface并使用config_db机制向下传递。 ::: image.png
image.png

搭建好以后的结构如上图所示