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    1. `timescale 1ns/1ns
    2. module data_minus(
    3. input clk,
    4. input rst_n,
    5. input [7:0]a,
    6. input [7:0]b,
    7. output reg [8:0]c
    8. );
    9. //**************code********************//
    10. always @(posedge clk or negedge rst_n) begin
    11. if(!rst_n) begin
    12. c <= 9'b0;
    13. end
    14. else begin
    15. if(a > b) begin
    16. c <= a - b;
    17. end
    18. else begin
    19. c <= b - a;
    20. end
    21. end
    22. end
    23. //**************code********************//
    24. endmodule