4.5 序列检测器（芯动笔试题）

:::info 用3段式状态机设计，请给出序列检测码10110的检测状态图和verilog code.除了状态机以外，还有其他的方法来监测这个序列？如果有的话，请画图或者使用文字说明。 :::

module detect_sequence(
  input clk,
  input reset_n,
  input data,
  output check,
);
  reg [5:0] current_state;
  reg [5:0] next_state;
  parameter idle = 6'b000000;
  parameter s0 = 6'b000001;
  parameter s1 = 6'b000010;
  parameter s2 = 6'b000100;
  parameter s3 = 6'b001000;
  parameter s4 = 6'b010000;
  always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
      current_state <= 1'b0;
    end
    else begin
      current_state <= next_state;
    end
  end
  always @(*) begin
    case(current_state)
      idle : next_state = (data == 1)? s0 : idle;
      s0 : next_state = (data == 1)? s0 : s1;
      s1 : next_state = (data == 1)? s2 : idle;
      s2 : next_state = (data == 1)? s3 : s1;
      s3 : next_state = (data == 1)? s1 : s4;
      s4 : next_state = (data == 1)? s0 : idle;
      default : next_state = idle;
    endcase
  end
  always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
      check <= 1'b0;
    end
    else begin
      if(next_state == s4) begin
        check <= 1'b1;
      end
    end
  end
endmodule