3.2 根据状态转移图实现时序电路

`timescale 1ns/1ns
module seq_circuit(
  input       C,
  input       clk,
  input       rst_n,
  output wire Y
);
  reg current_state;
  reg next_state;
  always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
      current_state <= 2'b00;
      next_state    <= 2'b00;
    end
    else begin
      current_state <= next_state;
    end
  end
  always @(*) begin
    case(current_state)
      2'b00 : next_state = (C == 1'b1)? 2'b01 : 2'b00;
      2'b01 : next_state = (C == 1'b1)? 2'b01 : 2'b11;
      2'b10 : next_state = (C == 1'b1)? 2'b10 : 2'b00;
      2'b11 : next_state = (C == 1'b1)? 2'b11 : 2'b10;
      default : next_state = 2'b00;
    endcase
  end
  assign Y = ((current_state == 2'b11) | ((current_state == 2'b10) && (C == 1)))? 1'b1: 1'b0;
endmodule